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? data device corporation 105 wilbur place bohemia, new york 11716 631-567-5600 fax: 631-567-7358 www.ddc-web.com for more information contact: technical support: 1-800-ddc-5757 ext. 7771 features ? wide bandwidth high carrier frequency programmable resolution: 10, 12, 14, or 16 bits high quality velocity output eliminates tachometer accuracy to 1.3 arc minutes synchro, resolver, or direct inputs synthesized reference eliminates 180 lock-up mil-prf-38534 processing available description the sdc-14580 series are versatile state-of-the-art synchro-to- digital (s/d) or resolver-to-digital (r/d) converters featuring pro- grammable resolution and a velocity output voltage. based on the popular sdc-14560 series, the sdc-14580 offers a higher carrier frequency of 1 to 5 khz and a higher bandwidth of 540 hz. tracking rate has also been increased and settling times decreased. resolution programming allows selection of 10, 12, 14, or 16 bits and are available with corresponding accuracies of up to 1 minute +1 lsb. resolution programming combines the high tracking rate of a 10-bit converter with the precision of a 16-bit device in one package. the velocity output (vel) from the sdc-14580 is a ground-based voltage of 0 to 10 vdc with a linearity of 2%. output voltage is positive for an increasing angle. the digital angle output from the sdc-14580 is a natural binary code, parallel positive logic and is ttl/cmos compat- ible. applications because of its high reliability, accuracy, small size, and low power consumption, the sdc-14580 series are ideal for the most stringent and severe industrial and military ground or avionics applications. military processing is available (consult factory). designed with three-state outputs, the sdc-14580 is especially well- suited for use with computer-based systems. among the many appli- cations are: radar and navigation systems, fire control systems, flight instrumentation, and flight trainers/simulators. sdc-14580 programmable synchro/resolver- to-digital converter make sure the next card you purchase has... ? 1990, 1999 data device corporation all trademarks are the property of their respective owners.
2 data device corporation www.ddc-web.com sdc-14580 h-05/04-0 figure 1. sdc-14580 block diagram s1 s2 s3 solid state synchro input option electronic scott t sin cos s1 s2 s3 solid state resolver input option electronic scott t sin cos s4 solid state resolver input option electronic scott t sin cos sin cos input options v internal dc reference reference conditioner synthesized ref demod bit detect error processor high accuracy control transformer input option 16 bit ct transparent latch 16 bit output transparent latch 3 state ttl buffer 3 state ttl buffer 16 bit u-d counter edge triggered latch vco inhibit transparent latch power supply conditioner digital angle +5 v inh em bits 1-8 bits 9-16 el s resolution control t 50 ns delay 0.4-1 s +10 v internal dc ref v (+5 v) +15 inh cb vel e bit +15 v -15 v diff gain of 2 diff gain of 2.75 vel u t e d r u t gain e sin ( - ) 1 lsb antijitter feedback ref in rl rh sin cos q ab
3 data device corporation www.ddc-web.com sdc-14580 h-05/04-0 table 1. sdc-14580 specifications these specifications apply over temperature range, power supply range, reference frequency, and amplitude range +10% signal amplitude variation and up to 10% harmonic distortion in the reference. parameter value comment resolution accuracy grades 10, 12, 14, or 16 bits 4, 2, or 1 minutes differential linearity repeatability 1 lsb max in the 16th bit 1 lsb max ref input characteristics voltage range carrier frequency ranges 10, 12, or 14 bit 16 bit input impedance single ended input differential common mode range 1-35 vrms 1-5 khz (full accuracy) 2-5 khz 50 kohm min 100 kohm min 50 v peak max 200 v transient peak up to 10 khz with reduced accuracy. signal input characteristics synchro zin line to line zin each line to ground common mode range resolver zin single ended zin differential zin each line to ground common mode range direct (2.0 v l-l) input signal type sin/cos range max voltage without damage input lmpedance 11.8 v l-l 17.5 kohm 11.5 kohm 60 v max 11.8 v l-l 23 kohm 46 kohm 23 kohm 60 v max 2 vrms nom, 2.2 vrms max 15 v continuous, 100 v peak transient zin > 20m//10 pf voltage options and minimum input impedance balanced. sin and cos resolver signals referenced to converter internal dc reference voltage, v. reference synthesizer sig/ref phase shift 60 typ, 45 min digital inputs logic type inputs max input voltage w/o damage loading inh (inhibit) en (enable bits 1-8) and el (enable bits 9-16) s (control transformer) resolution control 10 bit 12 bit 14 bit 16 bit logic 0 = 0.8 v max logic 1 = 2.0 v min -0.3 vdc to +8 vdc 10 a max b (pin 36) a (pin 35) 0 0 0 1 1 0 1 1 ttl/cmos compatible. pull-up current source to +5 v//5 pf max, cmos transient protected. logic 0 inhibits, logic 1 enables, data stable within 0.3 s. logic 0 enables, logic 1 high z within 100 ns, data valid within 150 ns. logic 0 for control transformer, logic 1 for normal tracking. unused output bits are at logic 0. digital outputs parallel data cb (converter busy) bit (built-ln-test) 10, 12, 14, or 16 bits 0.4 s to 1.0 s natural binary angle positive logic. positive pulse; leading edge indicates counter update. logic 0 for bit condition. pin programmable. max +1 lsb of selected resolution, see table 8 and ordering information.
4 data device corporation www.ddc-web.com sdc-14580 h-05/04-0 table 1. sdc-14580 specifications (continued) these specifications apply over temperature range, power supply range, reference frequency, and amplitude range; +10% signal amplitude variation and up to 10% harmonic distortion in the reference. parameter value comment digital outputs (continued) drive capability 50 pf plus rated logic drive. logic 0 logic 1 logic 0 logic 1 high z -1.6 ma at 0.4 v max 0.4 ma at 2.8 v min 100 mv max +5 v supply minus 100 mv min 10 a//5 pf max 1 ttl load 10 ttl loads driving cmos driving cmos analog outputs vel (velocity) e (ac error) 10 bit mode 12 bit mode 14 bit mode 16 bit mode load 50 mvrms 25 mvrms 12.5 mvrms 6.3 mvrms 3 kohm min see table 5, velocity characteristics. per lsb of error per lsb of error per lsb of error per lsb of error dynamic characteristics see table 7, dynamic characteristics. power supply characteristics nominal voltage and range max voltage w/o damage max current +15 vdc 5% +5 vdc 10% -15 vdc 5% +18 v +8 v -18 v 25 ma 10 ma 15 ma temperature ranges operating -30x -10x storage 0 c to +70 c -55 c to +125 c -65 c to +150 c physical characteristics size weight 1.9 x 0.78 x 0.21 inches (48.3 x 19.8 x 5.3 mm) 0.7 oz (20 gm) 36 pin ddip table 2. maximum ratings without damage parameter value comment all power (i.e., power supply and sig- nal inputs) should be removed from the circuit when adding or removing the converter. reference inputs 130 vrms direct signal inputs 15 v continuous, 100 v peak transient digital inputs -0.3 vdc to +8 vdc supply voltage +15 vdc +5 vdc -15 vdc +18 v +8 v -18 v storage temperature -65 c to 150 c lead temperature (soldering, ten seconds) 300 c thermal resistance: junction to case ( jc ) case to ambient ( ca ) 8 c/w 20 c/w
5 data device corporation www.ddc-web.com sdc-14580 h-05/04-0 theory of operation the sdc-14580 series are small, 36 pin ddip synchro-to-digital or resolver-to-digital hybrid converters. as shown in the block diagram (figure 1), the sdc-14580 can be broken down into the following functional parts: signal input option, converter, analog conditioner, power supply conditioner, and digital interface. converter operation as shown in figure 1, the converter section of the sdc-14580 contains a high accuracy control transformer, demodulator, error processor, voltage controlled oscillator (vco), up-down counter, and reference conditioner. the converter produces a digital angle which tracks the analog input angle to within the specified accuracy of the converter. the control transformer performs the following trigonometric computation: sin( - ) = sin cos - cos sin where: is angle theta representing the resolver shaft position. is digital angle phi contained in the up/down counter. the tracking process consists of continually adjusting to make ( - ) = 0, so that will represent the shaft position . the output of the demodulator is an analog dc level proportion- al to sin( - ). the error processor receives its input from the demodulator and integrates this sin( - ) error signal which then drives the vco. the vco?s clock pulses are accumulated by the up/down counter. the velocity voltage accuracy, linearity and off- set are determined by the quality of the vco. functionally, the up/down counter is an incremental integrator. therefore, there are two stages of integration which makes the converter a type ii tracking servo. in a type ii servo, the vco always settles to a counting rate which makes d /dt equal to d /dt without lag. the output data will always be fresh and available as long as the maximum tracking rate of the converter is not exceeded. the reference conditioner is a comparator that produces the square wave reference voltage which drives the demodulator. its single ended input z is 50k ohms min, 100k ohms differential. special functions reference synthesizer-quadrature voltages the synthesized reference section of the sdc-14580 eliminates errors caused by quadrature voltage. due to the inductive nature of synchros and resolvers, their signals typically lead the refer- ence signal (rh and rl) by about 6. when an uncompensated reference signal is used to demodulate the control transformer?s output, quadrature voltages are not completely eliminated. in a 12- or 14-bit converter it is not necessary to compensate for the reference signal?s phase shift. a 6 phase shift will, however, cause problems for the one minute accuracy converters. as shown in figure 1, the converter synthesizes its own cos( t+ ) reference signal from the sin -cos( t+ ), cos -cos( t + ) signal inputs and from the cos t reference input. the phase angle of the synthesized reference is determined by the signal input. the reference input is used to choose between the +180 and -180 phases. the synthesized reference will always be exactly in phase with the signal input, and quadrature errors will therefore be eliminated. the synthesized reference circuit also eliminates the 180 false error null hangup. quadrature voltages in a resolver or synchro are by definition the resulting 90 fundamental signal in the nulled out error voltage (e) in the converter. a digital position error will result due to the interaction of this quadrature voltage and a reference phase shift between the converter signal and reference inputs. the magni- tude of this error is given by the following formula: magnitude of error=(quadrature voltage/f.s.signal) tan( ) where: magnitude of error is in radians. quadrature voltage is in volts. full scale signal is in volts. = signal to ref phase shift an example of the magnitude of error is as follows: let: quadrature voltage = 11.8 mv let: f.s. signal = 11.8 v let: = 6 then: magnitude of error = 0.35 min ? 1 lsb in the 16th bit. note: quadrature is composed of static quadrature which is specified by the synchro or resolver supplier plus the speed voltage which is determined by the following formula: speed voltage=(rotational speed/carrier frequency) f.s. signal where: speed voltage is the quadrature due to rotation. rotational speed is the rps (rotations per second) of the synchro or resolver. carrier frequency is the ref in hz built-in-test (bit , pin 34) the built-in-test output (bit ) monitors the level of error (d) from the demodulator. d represents the difference in the input and output angles and ideally should be zero. if it exceeds approxi- mately 65 lsbs (of the selected resolution), the logic level at bit will change from a logic 1 to logic 0. this condition will occur dur- ing a large step and reset after the converter settles out. bit will
6 data device corporation www.ddc-web.com sdc-14580 h-05/04-0 also change to logic 0 for an over-velocity condition, because the converter loop cannot maintain input-output or if the converter malfunctions where it cannot maintain the loop at a null. bit will also be set if a loss-of-signal (los) and/or a loss-of-reference (lor) occurs. programmable resolution (a, pin 35; b, pin 36) resolution is controlled by two logic inputs, a and b (see table 3). the resolution can be changed during converter operation so the appropriate resolution and velocity dynamics can be changed as needed. to insure that a race condition does not exist between counting and changing the resolution, inputs a and b are latched internally on the trailing edge of cb (see figure 2). for more information refer to the accuracy and resolution section. note: all unused digital output data bits are at logic 0. special design considerations due to its high dynamic capability in 10- and 12-bit mode, the sdc-14580 series of converters has a potential for a spin- around condition. a spin-around condition occurs when the con- verter does not track and the angular input and the digital output a,b 0 s min cb 0.1 s min figure 2. resolution control timing diagram 30 90 150 210 270 330 360 (degrees) ccw in phase with rl-rh of converter and r2-r1 of cx. 0 s1-s3 = v sin max s3-s2 = v sin( + 120) max s2-s1 = v sin( + 240) max - v max + v max 30 90 150 210 270 330 360 (degrees) ccw in phase with rh-rl of converter and r2-r4 of rx. 0 s2-s4 = v cos max s1-s3 = ?v sin( ) max - v max + v max standard synchro control transmitter (cx) outputs as a function of ccw rotation from electrical zero (ez). figure 3. synchro and resolver signals standard resolver control transmitter (rx) outputs as a function of ccw rotation from electrical zero (ez) with r2-r4 excited. table 3. resolution control b (pin 36) a (pin 35) resolution 0 0 1 1 0 1 0 1 10 bit 12 bit 14 bit 16 bit continuously counts (spins) from 0 to 359.999. an indication of a spin-around condition is the digital output changing as the syn- chro or resolver input is stationary. during this time, the bit may flag an error condition and the velocity output may be at the max- imum positive or negative output voltage. this potential problem may happen at the time the unit is powered up, during a step, or during instantaneous acceleration. to avoid the spin-around condition when using the sdc-14580 converters in 10- or 12-bit mode, the following is required: 1) power up the sdc-14580 converter in either the 14- or 16- bit resolution mode and once it has settled change to the 10- or 12-bit mode. 2) avoid large steps and instantaneous accelerations. 3) if the dynamics required by the system do not exceed the dynamics of the sdc-14580 converter in the 14-bit mode, then set the unit for the 14-bit mode and disregard the additional lsbs. interfacing - input signal input options the sdc-14580 series offers three input options: synchro, resolver, or direct resolver input. in a synchro or resolver, shaft angle data is transmitted as the ratio of carrier amplitudes across the input terminals. synchro signals, which are of the form sin ? cos t, sin( +120)cos t, and sin( +240)cos t are internally
7 data device corporation www.ddc-web.com sdc-14580 h-05/04-0 reference oscillator parallel data sdc-14580 stator rotor s3 s1 s2 s2 s1 s3 r4 r2 lo hi rh vel (velocity) inh (inhibit) cb (count) rl s4 s4 el em reference oscillator parallel data sdc-14580 stator rotor sin cos s2 s1 s3 r4 r2 lo hi rh vel (velocity) inh (inhibit) cb (count) rl v s4 el em figure 5. resolver input connection diagram figure 6. direct input connection diagram reference oscillator parallel data sdc-14580 stator rotor s3 s1 s2 s2 s1 s3 el em r2 r1 lo hi rh vel (velocity) inh (inhibit) cb (count) rl figure 4. synchro input connection diagram
8 data device corporation www.ddc-web.com sdc-14580 h-05/04-0 converted to resolver format; sin cos t and cos cos t. direct resolver inputs accept 2.0 vrms inputs in resolver form, (sin ? cos t and cos cos t) and are buffered prior to conversion. fig- ure 3 illustrates synchro and resolver signals as a function of the angle . the solid-state signal and reference inputs are true differential inputs with high ac and dc common mode rejection. input impedance is maintained with power off. the synchro and resolver input options are shown in figures 4 and 5. the direct resolver inputs are transient protected voltage followers which accept 2.0 vrms resolver inputs as shown in figure 6. resistor programming for non-standard input voltages when applying voltages greater than 2.0 vrms to the direct input option, a simple voltage divider can be used to attenuate both the sin and cos inputs. since the converter inputs are voltage followers there will be no loading on the resistor dividers. (see figure 7.) the resolver input conditioner consists of two differential ampli- fiers. the input is currently scaled down with 23 kohm resistors for the 11.8 v resolver. when applying resolver input voltages greater than the rated voltages, four additional resistors are used to scale down the voltage. these resistors are placed one in series with each input line (see figure 8). interfacing - digital outputs and controls digital interface the digital interface circuitry performs three main functions: 1. latches the output bits during an inhibit (lnh ) command allowing stable data to be read out of the sdc-14580. 2. furnishes parallel tri-state data formats. 3. acts as a buffer between the internal cmos logic and the external ttl logic. in the sdc-14580 applying an inhibit (inh ) command will lock the data in the inhibit transparent latch without interfering with the continuous tracking of the converter?s feedback loop. therefore the digital angle is always updated, and the inh can be applied for an arbitrary amount of time. the inhibit transparent latch and the 50 ns delay are part of the inhibit cir- cuitry. for further information see the inhibit (inh , pin 33) paragraph. digital angle outputs (logic input/output) the digital angle outputs are buffered and provided in a two-byte format. the first byte contains the msbs (bits 1-8) and is enabled by placing em (pin 26) to a logic 0. depending on the user-pro- grammed resolution, the second byte contains the lsbs and is enabled by placing el (pin 25) to a logic 0. 1 r1 s3 sdc-14580 s3 2 r2 s1 s1 3 r3 s2 s2 4 r4 s4 s4 figure 8. resolver input connection diagram 2 r3 3 r1 s3 sdc-14580 r4 1 r2 s1 s2 s4 cos sin v figure 7. direct input resistor scaling input v oltage l-l r1+r3 = 1v r3 notes: (1) r1 = r2; r3 = r4 to 0.1% match. (2) r1 + r3 and r2 + r4 should be as high as possible to minimize resolver loading. r + 23k input v oltage l-l = 23k 11.8 v notes: (1) input voltage l-l is greater than 11.8 v. (2) r = r1 = r2 = r3 = r4 to 0.1% match. figure 9. tri-state output timing 100 ns max em or el 150 ns max data data valid high z high z
9 data device corporation www.ddc-web.com sdc-14580 h-05/04-0 the second byte will contain either bits 9-10 (10-bit resolution), bits 9-12 (12-bit resolution), bits 9-14 (14-bit resolution), or bits 9-16 (16-bit resolution). all unused lsbs will be at logic 0. table 4 lists the angular weight for the digital angle outputs. the digital angle outputs are valid 150 ns after em or el are acti- vated with a logic 0 and are high impedance within 100 ns, max after em and el are set to logic 1 (see figure 9). both enables are internally pulled up to +5 v // 5 pf max current sources. digital angle output timing the digital angle outputs 10, 12, 14, or 16 parallel data bits and converter busy (cb). all logic outputs are short-circuit proof to ground and +5 v. the cb output is a positive, 0.4 to 1.0 s pulse. the digital output data changes approximately 50 ns after the leading edge of the cb pulse because of an internal delay. data is valid 0.2 s after the leading edge of cb (see figure 10). the angle is determined by the sum of the bits at logic 1. the dig- ital outputs are valid 150 ns max after em or el go low and are high impedance within 100 ns max of em or el going high. inhibit (inh , pin 33) when an inhibit (inh ) input is applied to the sdc-14580, the output transparent latch is locked causing the output data bits to remain stable while data is being transferred. (see figure 11.) the output data bits are stable 0.5 s after inh goes to logic 0. a logic 0 at the t input of the inhibit transparent latch latches the data, and a logic 1 applied to t allows the bits to change. this latch also prevents the transmission of invalid data when there is an overlap between cb and inh . while the counter is not being updated, cb is at logic 0 and the inh latch is transparent; when cb goes to logic 1, the inh latch is locked. if cb occurs after inh has been applied, the latch will remain locked and its data will not figure 12. output data update timing data 0 - 1 s inh 100 ns min 2 s min update stable stable figure 11. inhibit timing diagram data valid 0.5 s asynchronous to cb inh figure 10. converter busy timing diagram data 0.4 - 1.0 s min cb 0.2 s min 1.5 s min depends on d /dt valid table 4. digital angle outputs bit deg/bit min/bit 1 (msb all modes) 2 3 4 5 6 7 8 9 10 (lsb 10 bit mode) 11 12 (lsb 12 bit mode) 13 14 (lsb 14 bit mode) 15 16 (lsb 16 bit mode) 180 90 45 22.5 11.25 5.625 2.8125 1.4063 0.7031 0.3516 0.1758 0.0879 0.0439 0.0220 0.0110 0.0055 10800 5400 2700 1350 675 337.5 168.75 84.38 42.19 31.09 10.55 5.27 2.64 1.32 0.66 0.33 note: em enables the 8 msbs and el enables the lsbs.
10 data device corporation www.ddc-web.com sdc-14580 h-05/04-0 change until cb returns to logic 0; if inh is applied during cb, the latch will not lock until the cb pulse is over. the purpose of the 50 ns delay is to prevent a race condition between cb and inh where the up-down counter begins to change as an inh is applied. an inh input, regardless of its duration, does not affect the con- verter update. a simple method of interfacing to a computer asynchronous to cb is: (1) apply lnh ; (2) wait 0.5 s min; (3) transfer the data; (4) release inh . a logic 1 for the lnh enables the output data to be updated. the time it takes for inh to go to a logic 1 should be 100 ns minimum before valid data is transferred. to allow the update of the output data with valid information the inh must remain at a logic 1 for 1 s minimum (see figure 12). data transfers digital output data from the sdc-14580 can be transferred to 8- bit and 16-bit bus systems. for 8-bit systems, the msb and lsb bytes are transferred sequentially. for 16-bit systems all bits are transferred at the same time. data transfer to 8-bit bus figures 13 and 14 show the connections and timing for trans- ferring data from the sdc-14580 to an 8-bit bus. as can be seen by the timing diagram the following occurs: 1. the converter inh control is applied and must remain low for a minimum of 500 ns before valid data is transferred. 2. em is set to a low state (logic 0) 150 ns min after inh goes low and must remain low for a minimum of 150 ns before the msb data (1-8) is valid and transferred. 3. as em is set to a high state (logic 1), el is brought low for 150 ns min before the lsb data is valid and transferred. 4. el should go high (to logic 1) at least 100 ns max before another device uses the bus. 5. inh goes high and data transfer is done and the data refresh cycle can begin. note the time it takes for inh to go to a logic 1 should be 100 ns minimum before valid data is transferred. note: for further understanding refer to the beginning of this section (i.e., digital interface, digital angle outputs, digital angle output timing, and inhibit). 16-bit data transfer data transfer to the 16-bit bus is much simpler than the 8-bit bus. figures 15 and 16 show the connections and timing for trans- ferring data from the sdc-14580 to a 16-bit bus. as can be seen by the timing diagram (figure 16) the follow- ing occurs: 1. the converter inh control is applied and must remain low for a minimum of 500 ns before valid data is transferred. 2. em and el are set to a low state (logic 0) 150 ns min after inh goes low and must remain low for a minimum of 150 ns before the data (1-16) is valid and transferred. 3. em and el should go high (to logic 1) at least 100 ns max before another device uses the bus. 4. inh goes high and data transfer is done and the data refresh cycle can begin. note the time it takes for inh to go to a logic 1 should be 100 ns minimum before valid data is transferred. note: for further understanding refer to the beginning of this section (i.e., digital interface, digital angle outputs, digital angle output timing, and inhibit). interfacing - analog outputs the analog outputs are ac error (e), internal dc reference voltage, and velocity (vel). ac error (e, pin 27) ac error out (e) is used in ct mode. the ac error is propor- tional to the difference between the input angle and the digital input angle , ( - ), with a scaling of: 50 mv rms/lsb (10-bit mode) 25 mv rms/lsb (12-bit mode) 12.5 mv rms/lsb (14-bit mode) 6.3 mv rms/lsb (16-bit mode) table 5. velocity characteristics parameter units typ max polarity output voltage voltage scaling scale factor scale factor tc reversal error reversal error tc linearity linearity tc zero offset zero offset tc load v rps/v % ppm/c % ppm/c % output ppm/c mv v/c kohms 13 5 100 1 25 1 25 15 25 ? 10 min 10 200 2 50 2 50 40 50 3 min table 6. voltage scaling resolution (values in rps/volt) 10 bit 12 bit 14 bit 16 bit 80 20 5 1.25 note: if the resolution is changed while the input is changing, then the velocity output voltage and the digital output will have a transient until it settles to the new velocity scaling at a speed determined by the bandwidth. if additional information is required, consult the factory. positive for increasing angle see voltage scaling table 6
11 data device corporation www.ddc-web.com sdc-14580 h-05/04-0 sdc-14580 16 bit bus (msb) bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 bit 8 bit 9 bit 10 bit 11 bit 12 bit 13 bit 14 bit 15 (lsb) bit 16 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 el em inh sdc-14580 8 bit bus (msb) bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 bit 8 bit 9 bit 10 bit 11 bit 12 bit 13 bit 14 bit 15 (lsb) bit 16 d7 d6 d5 d4 d3 d2 d1 d0 el em inh inh data 1-16 valid 500 ns min 150 ns min 0 ns min 100 ns max em, el inh data 1-8 valid data 9-16 valid 500 ns min 150 ns min 0 ns min 100 ns max 150 ns min 0 ns min 100 ns max el em figure 14. 8-bit data transfer timing figure 16. 16-bit data transfer timing figure 13. 8-bit data transfer figure 15. 16-bit data transfer
12 data device corporation www.ddc-web.com sdc-14580 h-05/04-0 the error is positive if it is in phase with the reference and neg- ative if it is out of phase with the reference. the e output can swing 10 v min with respect to ground when the voltage level of the 15 v power supplies are 15 v. the out- put level range changes proportionally with the power supply level. internal dc reference voltage (v, pin 1) this internal voltage is not required externally for normal opera- tion of the converter. it is used as the internal dc reference com- mon with the direct input option. it is nominally +5 v and is pro- portional to the +15 vdc supply. velocity (vel, pin 23) the velocity output (vel, pin 23) is a dc voltage proportional to angular velocity d /dt. the velocity is the input to the voltage con- trolled oscillator (vco), as shown in figure 1. its linearity and accuracy are dependent solely on the linearity and accuracy of the vco. the vel output can swing 10 v with respect to ground when the voltage level of the 15 v power supplies are 15 v. the out- put level range changes proportionally with the power supply level. the analog output vel characteristics are listed in tables 5 and 6. the vel output has dc tachometer quality specifications such that it can be used as the velocity feedback in servo applications. vel filtered 91k vel 0.01 f = rc = 1/a figure 17. vel output filter error processor input open loop transfer function = output where: 2 a = a a 1 2 velocity out digital position out ( ) vco ct s a + 1 1 b s s + 1 10b h = 1 s a + 1 1 b 2 s s + 1 10b + - e a 2 s 2.75 -12 db/oct 4 ba (bw) 2a -6 db/oct 10b (rad/sec) figure 19. open loop bode plot figure 18. transfer function block diagram 2a 2 2 a (rad/sec) closed loop bw (hz) = 2 a figure 20. closed loop bode plot table 7. dynamic characteristics parameter units bandwidth resolution bits 10 12 14 16 input freq. khz 1-5 1-5 1-5 2-5 tracking rate bandwidth k a a 1 a 2 a b acc - 1 lsb lag settling time rps min hz 1/sec 2 1/sec 1/sec 1/sec 1/sec deg/sec 2 ms max 800 540 1.5m 6.2 200k 1.2k 600 512k 15 200 128k 20 50 32k 35 12.5 8k 70 same as value to left overshoot small signal settling time max slope equals tracking rate (slew rate) 2 1 figure 21. response to a step input note: for 400 hz and 60 hz reference frequencies, use sdc-14560 series converters.
13 data device corporation www.ddc-web.com sdc-14580 h-05/04-0 when the resolution is changed, the vel scaling is also changed. since the vel output is from an integrator with a capacitor feedback, the vel voltage cannot change instanta- neously. therefore, when changing resolution while moving, there will be a transient with a magnitude proportional to the velocity and a duration determined by the converter bandwidth. special applications control transformer (ct) mode the sdc-14580 can also be used as a control transformer (ct). the ct mode is used when the ac error (e) is needed to drive an external control loop by the difference angle of the ana- log input and the digital input. it is also used for presetting the converter to a specific angle to reduce the step response time. referring to the equation below, the output is an ac voltage (e) which varies as the sine of the difference between the analog input angle and the digital angle. e = sin( - ) cos t this is analogous to the function of the rotary control transformer except in this case the rotary shaft input is replaced by a digital signal. figure 22 illustrates the ct block diagram. the ct mode is enabled by placing s (pin 30) to a logic 0 and by using the digi- tal output lines (now bidirectional) as digital inputs. when the sdc-14580 functions as a ct the digital inputs are double buffered, em is redefined as lm (latch msbs), el is redefined as ll (latch lsbs) and inh becomes la (latch all). control transformers are frequently used as error signal genera- tors in closed servo loops. the ct mode can be applied in servo systems, as shown in figure 23. in this application, changes in position are commanded by the microcomputer through signals fed to the ct. the ct then drives the motors through dc power amplifiers. using the sdc-14580 as an s/d with vel to stabilize position loop figure 24 illustrates a typical use of a sdc-14580 connected as an s/d using the vel output to stabilize the position loop. connecting the sdc-14580 to a pc board the sdc-14580 can be attached to a pc board using hand sol- der or wave soldering techniques. limit exposure to 300c (572f) max, for 10 seconds maximum. since the sdc-14580 series converters contain a cmos device, standard cmos handling procedures should be fol- lowed. velocity response a filter on the vel output will, for a step input in velocity, elimi- nate the velocity overshoot (normally critically damped) and filter carrier frequency ripple. the vel filter is shown in figure 17. interfacing - dynamic performance a type ii servo loop (k v = ) and very high acceleration con- stants give the sdc-14580 superior dynamic performance. if the power supply voltages are not the +5 vdc nominal value, the specified input rates will increase or decrease in proportion to the fractional change in voltage. transfer functions the dynamic performance of the converter can be determined from its transfer function block diagram (figure 18) and open and closed loop bode plots (figures 19 and 20). values for the transfer function block can be obtained from table 7. response parameters as long as the converter maximum tracking rate is not exceed- ed, there will be no velocity lag in the converter output although momentary acceleration errors remain. if a step input occurs, as when the power is initially applied, the response will be critically damped. figure 21 shows the response to a step input. after initial slewing at the maximum tracking rate of the converter, there is one overshoot (which is inherent in a type ii servo). the overshoot settling to a final value is a function of the small signal settling time. accuracy and resolution table 8 lists the total accuracy including quantization for the various resolution and accuracy grades. faster settling time using bit to reduce resolution since the sdc-14580 has higher precision in the higher resolu- tion mode and faster settling in the lower resolution modes, the bit output can be used to program the sdc-14580 for lower res- olution, allowing the converter to settle faster for step inputs. high precision, faster settling can therefore be obtained simulta- neously and automatically in one unit. table 8. accuracy / resolution accuracy (minutes) accuracy / resolution 10 bit 12 bit 14 bit 16 bit 1 + 1 lsb 2 + 1 lsb 6 + 1 lsb 4 + 1 lsb 22.1 23.1 25.1 27.1 6.3 7.3 9.3 11.3 2.3 3.3 5.3 7.3 1.3 2.3 4.3 6.3
14 data device corporation www.ddc-web.com sdc-14580 h-05/04-0 s1 s2 s3 solid state synchro input option electronic scott t sin cos s1 s2 s3 solid state resolver input option electronic scott t sin cos s4 solid state resolver input option electronic scott t sin cos sin cos input options v internal dc reference reference conditioner synthesized ref demod bit detect high accuracy control transformer input option 16 bit ct transparent latch 16 bit u-d counter power supply conditioner resolver input +5 v lm(em) resolution control +10 v internal dc ref v (+5 v) +15 bit e d r gain e sin ( - ) rl rh sin cos ab diff gain of 2 ll(el) +15 v -15 v 1-8 9-16 la(inh) digital angle figure 22. ct mode block diagram amp demodulator computer sdc-14580 as a ct ref synchro e s figure 23. ct mode application figure 24. converter with vel to stabilize position amp computer con- verter ref source synchro d/a vel
15 data device corporation www.ddc-web.com sdc-14580 h-05/04-0 s1 1 s2 2 s3 3 s4 4 b1 5 b2 6 b3 7 b4 8 b5 9 b6 10 b7 11 b8 12 b9 13 b10 14 b11 15 b12 16 b13 17 b14 18 36 b 35 a 34 bit 33 inh 32 +15 v 31 -15 v 30 s 29 gnd 28 +5 v 27 e 26 em 25 el 24 cb 23 vel 22 b16 21 b15 20 rl 19 rh figure 25. sdc-14580 pin locations table 9. sdc-14580 pin functions pin no. title i/o function 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 i i i i o o o o o o o o o o o o o o i i o o o o i i o i ? i i i o o i i (s)=synchro input; (r)=resolver input; (x)=direct input (s)=synchro input; (r)=resolver input; (x)=direct input (s)=synchro input; (r)=resolver input; (x)=direct input (r)=resolver input digital output bit 1 (msb) digital output bit 2 digital output bit 3 digital output bit 4 digital output bit 5 digital output bit 6 digital output bit 7 digital output bit 8 digital output bit 9 digital output bit 10 (lsb - 10-bit mode) digital output bit 11 digital output bit 12 (lsb - 12-bit mode) digital output bit 13 digital output bit 14 (lsb - 14-bit mode) ac reference input. used to drive internal demodulator ac reference input. used to drive internal demodulator digital output bit 15 digital output bit 16 (lsb - 16-bit mode) velocity. dc voltage proportional to angular velocity converter busy. indicates digital output update. enable lsbs. logic 0 enables digital output bits 9-16. logic 1 disables these bits. enable msbs. logic 0 enables digital output bits 1-8. logic 1 disables these bits. ac error. used in ct mode; e is proportional to the difference between the input angle and the digital input angle ( - ). supply voltage ground control transformer set. logic 1 for normal tracking; logic 0 for ct operation. used when ac error (e) is needed to drive external control loop by the difference angle of the resolver input and the dig- ital input and for presetting the converter to a specific angle to reduce the step response time. supply voltage supply voltage inhibit. logic 0 prevents digital output bits from changing. built-ln-test. monitors level of error (d) and will change to logic 0 if it exceeds 65 bits approx. also logic 0 for an over-velocity condition. resolution control. changes resolution during converter operation to 10, 12, 14, or 16 bits depen- dent on logic level. resolution control. changes resolution during converter operation to 10, 12, 14, or 16 bits depen- dent on iogic level. s1(s) s1(r) v(x) s2(s) s2(r) +c(x) s3(s) s3(r) +s(x) s4(r) b1 b2 b3 b4 b5 b6 b7 b8 b9 b10 b11 b12 b13 b14 rh rl b15 b16 vel cb el em e +5 v gnd s -15 v +15 v inh bit a b top view
16 data device corporation www.ddc-web.com sdc-14580 h-05/04-0 1.895 0.005 (48.1 0.13) 1.700 0.005 (43.2 0.13) 0.018 (0.46) diam typ 0.100 typ(2.54) tol. non- cumulative 0.21 max (5.3) dot identifies pin 1 0.775 0.005 (19.7 0.13) 0.600 0.005 (15.2 0.13) 0.09 0.01 (2.3 0.25) 0.10 0.01 (2.5 0.3) side view bottom view 0.25 min (6.4) 0.015 max (0.39) seating plane 0.055 (1.4) rad typ 0.086 typ radius *note 6 0.020 (0.508) diam max notes: 1. dimensions shown are in inches (mm). 2. lead identification numbers are for reference only. 3. lead cluster shall be centered within 0.01 (0.25) of outline dimensions. lead spacing dimensions apply only at seating plane. 4. package is kovar with electroless nickel plating. 5. case is electrically floating. 6. after pre-tinning diameter maximum is 0.021 figure 26. sdc-14580 mechanical outline 36-pin ddip
17 data device corporation www.ddc-web.com sdc-14580 h-05/04-0 ordering information sdc-1458x-xxxx supplemental process requirements: s = pre-cap source inspection l = 100% pull test q = 100% pull test and pre-cap source inspection k = one lot date code w = one lot date code and pre-cap source inspection y = one lot date code and 100% pull test z = one lot date code, pre-cap source inspection and 100% pull test blank = none of the above accuracy: 2 = 4 minutes + 1 lsb 4 = 2 minutes + 1 lsb 5 = 1 minute + 1 lsb process requirements: 0 = standard ddc processing, no burn-in (see table below.) 1 = mil-prf-38534 compliant 2 = b* 3 = mil-prf-38534 compliant with pind testing 4 = mil-prf-38534 compliant with solder dip 5 = mil-prf-38534 compliant with pind testing and solder dip 6 = b* with pind testing 7 = b* with solder dip 8 = b* with pind testing and solder dip 9 = standard ddc processing with solder dip, no burn-in (see table below.) temperature grade/data requirements: 1 = -55c to +125c 2 = -40c to +85c 3 = 0c to +70c 4 = -55c to +125c with variables test data 5 = -40c to +85c with variables test data 8 = 0c to +70c with variables test data configuration: 0 = 11.8v, synchro 5 = 11.8v, resolver 7 = 2 v, direct resolver notes: for 400 hz and 60 hz reference frequencies use the sdc-14560 series converters. drawings to desc format available from factory. * standard ddc processing with burn-in and full temperature test?see table below. table 1 1015 (note 1) , 1030 (note 2) burn-in notes: 1. for process requirement "b*" (refer to ordering information), devices may be non-compliant with mil- std-883, test method 1015, paragraph 3.2. contact factory for details. 2. when applicable. 3000g 2001 constant acceleration c 1010 temperature cycle a and c 1014 seal ? 2009, 2010, 2017, and 2032 inspection condition(s) method(s) mil-std-883 test standard ddc processing for hybrid and monolithic hermetic products
18 h-05/04-0 printed in the u.s.a. the information in this data sheet is believed to be accurate; however, no responsibility is assumed by data device corporation for its use, and no license or rights are granted by implication or otherwise in connection therewith. specifications are subject to change without notice. please visit our web site at www.ddc-web.com for the latest information. 105 wilbur place, bohemia, new york, u.s.a. 11716-2482 for technical support - 1-800-ddc-5757 ext. 7771 headquarters, n.y., u.s.a. - tel: (631) 567-5600, fax: (631) 567-7358 southeast, u.s.a. - tel: (703) 450-7900, fax: (703) 450-6610 west coast, u.s.a. - tel: (714) 895-9777, fax: (714) 895-4988 united kingdom - tel: +44-(0)1635-811140, fax: +44-(0)1635-32264 ireland - tel: +353-21-341065, fax: +353-21-341568 france - tel: +33-(0)1-41-16-3424, fax: +33-(0)1-41-16-3425 germany - tel: +49-(0)8141-349-087, fax: +49-(0)8141-349-089 japan - tel: +81-(0)3-3814-7688, fax: +81-(0)3-3814-7689 world wide web - http://www.ddc-web.com data device corporation registered to iso 9001 file no. a5976 r e g i s t e r e d f i r m ? u

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